Phase Error Cancellation

摘要

A noise cancellation signal is generated for a fractional-N phase-locked loop ( 200 ). A divide value is provided to a first delta sigma modulator circuit ( 203 ), which generates a divide control signal to control a divide value of a feedback divider ( 208 ) in the phase-locked loop. An error term (e) is generated that is indicative of a difference between the generated divide control signal and the divide value supplied to the first delta sigma modulator circuit. The error term is integrated in an integrator ( 320 ) to generate an integrated error term (x), where x^k+1=x^k+e^k; and a phase error correction circuit ( 209 ) utilizes the error term e^k and the integrated error term x^k to generate the phase error cancellation signal.