发明名称 DATA TRANSMISSION CIRCUIT AND DATA TRANSMISSION/RECEPTION SYSTEM
摘要 <p>A data transmission circuit for converting a parallel data signal into a serial data signal for transmission comprises a clock generation circuit, an output circuit, and a shift register circuit in order to perform the data transmission/reception between internal elements without fail regardless of improved data transfer rate, increased manufacturing variations, fluctuations in a power supply voltage or temperature, or the like. The clock generation circuit generates a clock signal. The output circuit is set up to output the serial data signal. The shift register circuit captures the parallel data signal and sequentially transfers the captured parallel data signal to the output circuit bit-by-by in a shift operation synchronized with the clock signal of the clock generation circuit.</p>
申请公布号 WO2008105053(A1) 申请公布日期 2008.09.04
申请号 WO2007JP53534 申请日期 2007.02.26
申请人 FUJITSU LIMITED;YAMAGUCHI, HISAKATSU 发明人 YAMAGUCHI, HISAKATSU
分类号 H03M9/00 主分类号 H03M9/00
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