发明名称 DATA PROCESSOR AND MEMORY READ ACTIVE CONTROL METHOD
摘要 Instruction cache memory having a plurality of memory (for example, cache WAY), means 3 for storing prediction data of a conditional branch of a branch instruction being taken or not taken and for storing prediction data of memory storing the branch instruction data of the plurality of memory when the prediction is the branch being taken, and means for, when an instruction to be executed is a branch instruction, outputting a read active control signal to the plurality of memories 1 by using two pieces of prediction data obtained from the means by an index corresponding to the branch instruction, are comprised.
申请公布号 US2008215865(A1) 申请公布日期 2008.09.04
申请号 US20080040269 申请日期 2008.02.29
申请人 FUJITSU LIMITED 发明人 HINO MITSUAKI;YAMAZAKI YASUHIRO
分类号 G06F9/32 主分类号 G06F9/32
代理机构 代理人
主权项
地址