发明名称 Vertical metal line of Semiconductor device and the Fabricating Method thereof
摘要 <p>A semiconductor device and method for manufacturing the same are disclosed. A semiconductor device according to an embodiment comprises an interlayer insulating layer including a lower conductor wiring layer and a via hole exposing the lower conductor wiring layer, a conductor material filled inside the via hole, and an upper conductor wiring layer electrically connected to the lower conductor wiring layer through the conductor material filled inside the via hole. A barrier layer for inhibiting a loss of the conductor material filled inside the via hole is formed with a portion filling the upper portion of the via hole, and the upper conductor wiring layer is formed on the barrier layer.</p>
申请公布号 KR100857009(B1) 申请公布日期 2008.09.04
申请号 KR20060135793 申请日期 2006.12.28
申请人 发明人
分类号 H01L21/28 主分类号 H01L21/28
代理机构 代理人
主权项
地址