| 摘要 |
The sleep watchdog circuit for asynchronous circuits of the present invention contains clock means, counting means with multiple trigger input function and a digital supply. When the circuit is in the normal operation state, a periodic reset or activity signal is present that will reset the watchdog counter. As a result the clock means will keep on running, and the digital supply is operating in "normal" mode. When the circuit is put into the "sleep/standby" state, the "activity" signal becomes inactive, and if no wakeup events occur before the counter is finished the clock means will be put to a halt and the digital supply changes into a low power mode.
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