发明名称 |
PSEUDO-DUAL PORT MEMORY WHERE RATIO OF FIRST TO SECOND MEMORY ACCESS IS CLOCK DUTY CYCLE INDEPENDENT |
摘要 |
A pseudo-dual port memory performs both a first memory access operation and a second memory access operation in a single period of an externally supplied clock signal CLK. The signal CLK is used to latch a first address for the first operation and a second address for the second operation. Control circuitry generates first control signals that initiate the first operation. The time duration of the first operation depends upon a delay through a delay circuit. A precharge period follows termination of the first operation. The time duration of the precharge period depends upon a propagation delay through the control circuit. The memory access of the second operation is initiated following termination of the precharging. The time duration of the second memory access depends on a delay through the delay circuit. The time when the second operation is initiated is independent of the duty cycle of CLK.
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申请公布号 |
KR20080080548(A) |
申请公布日期 |
2008.09.04 |
申请号 |
KR20087014525 |
申请日期 |
2006.11.17 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
JUNG, CHANG HO |
分类号 |
G11C11/4193;G11C7/10;G11C7/22 |
主分类号 |
G11C11/4193 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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