| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the formation area of a CMOS inverter circuit using a vertical transistor. <P>SOLUTION: pMOS and nMOS transistors Tr1 and Tr2 in which p-type and n-type impurity regions 1p and 1n are formed on an element forming region 5 defined by an insulated separation band 2 and which use the regions as drain regions and use a nanowire 3 provided on the drain regions as a channel are provided on a semiconductor substrate 1. A connection region 4 in ohmic contact with the impurity regions 1p and 1n is formed on the front surface of the element forming region 5. The connection region 4 is connected with an output signal via 16 on the outside of the transistors Tr1 and Tr2. Further, an input signal via 17 is connected to gate electrode wiring 15 to which a gate electrode 13 is connected of the transistors Tr1 and Tr2. If there is a region for forming the two transistors and the two via holes, the CMOS circuit can be formed. <P>COPYRIGHT: (C)2008,JPO&INPIT |
