LOCALIZED TEMPERATURE CONTROL DURING RAPID THERMAL ANNEAL

摘要

Disclosed herein are embodiments of a semiconductor structure 100- 400 and an associated method of forming the semiconductor structure 100-400 with shallow trench isolation structures 120 having selectively adjusted reflectance and absorption characteristics in order to ensure uniform temperature changes across a wafer during a rapid thermal anneal and, thereby, limit variations in device performance. Also disclosed are embodiments of another semiconductor structure 700a-b and an associated method of forming the semiconductor structure 700a-b with devices having selectively adjusted reflectance and absorption characteristics in order to either selectively vary the performance of individual devices (e.g., to form devices with different threshold voltages (Vt) on the same wafer) and/or to selectively optimize the anneal temperature of individual devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals).