| 摘要 |
An interrupt controller (2) is provided with priority registers (6) storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit (10) provides multiple mappings to the priority values stored in dependence upon the priority value manager (16, 18), seeking to make an access. In this way, a first priority value manager (18), such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager (16), such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level. |
