| 摘要 |
PROBLEM TO BE SOLVED: To provide an A/D converter which has large phase margin and is capable of stable data import. SOLUTION: In data clocks Ca to Cd which are output each from A/D converters 22(1) to 22(4) together with data signals Da to Dd, the data clocks Ca, Cc of odd-numbered sampling order are latched by latch circuits 26(1), 26(3) as they are, and latch output thereof is output to a memory part 28 as write enable signals Ea, Ec. As for data clocks Cb, Cd of even-numbered sampling order, inversion output thereof is latched by latch circuits 26(2), 26(4), and latch output thereof is output to the memory part 28 as write enable signals Eb, Ed. Each data is subjected to memory treatment, thereby generating phase margin of (N/2+1)/N of a period of the data clock. COPYRIGHT: (C)2008,JPO&INPIT
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