| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device having small circuit scale without delaying read/write operation. SOLUTION: The semiconductor memory device is provided with memory cells MC storing data according to the number of majority carriers in a floating body, word lines WL connected to gates of the memory cells, a pair of bit lines BLL, bBLL transmitting data of the memory cells, a pair of sense nodes SN, bSN connected to the pair of bit lines and transmitting data of the memory cells, a plurality of transfer gates TGL1, TGL2 connected between the pair of bit lines and the pair of sense nodes, latch circuits LC1, LC2 latching a high level potential VBLH to one of the pair of sense nodes and latching a first low level potential VSS1 to the other, and level shifter LS1, LS2 applying a second low level potential VSS2 being lower than the first low level potential VSS1 to one of the pair of bit lines in accordance with a potential latched to the pair of sense nodes during data write/rewrite. COPYRIGHT: (C)2008,JPO&INPIT
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