| 摘要 |
PROBLEM TO BE SOLVED: To perform circuit verification with consideration of meta-stability in a short verification time. SOLUTION: A CDC part detection part 102 detects a CDC part in which circuit parts operating with different clock signals are mutually connected from a circuit to be verified, a delay generator embedding part 104 embeds a delay generator to which signal delay can be selectively set to the detected CDC part, and a simulation execution part 107 simulates the circuit with the delay generator set not to delay the signal, using a predetermined scenario. A delay generation pattern creation part 109 creates a delay generation pattern of signal delay which affects the output signal of the circuit by receiving the result of the executed simulation and the circuit with the delay generator, and a verification part 111 selects whether to delay the signal by the delay generator according to the created delay generation pattern to verify the operation of the circuit. COPYRIGHT: (C)2008,JPO&INPIT
|
