发明名称 Memory Device and Semiconductor Integrated Circuit
摘要 First electrode layer includes a plurality of first electrode lines (W 1 , W 2 ) extending parallel to each other. State-variable layer lying on the first electrode layer includes a plurality of state-variable portions ( 60 - 11, 60 - 12, 60 - 21, 60 - 22 ) which exhibits a diode characteristic and a variable-resistance characteristic. Second electrode layer lying on the state-variable layer includes a plurality of second electrode lines (B 1 , B 2 ) extending parallel to each other. The plurality of first electrode lines and the plurality of second electrode lines are crossing each other when seen in a layer-stacking direction with the state-variable layer interposed therebetween. State-variable portion ( 60 - 11 ) is provided at an intersection of the first electrode line (W 1 ) and the second electrode line (B 1 ) between the first electrode line and the second electrode line.
申请公布号 US2008212359(A1) 申请公布日期 2008.09.04
申请号 US20060883653 申请日期 2006.04.21
申请人 MURAOKA SHUNSAKU;OSANO KOICHI;MITANI SATORU;SEKI HIROSHI 发明人 MURAOKA SHUNSAKU;OSANO KOICHI;MITANI SATORU;SEKI HIROSHI
分类号 G11C11/21 主分类号 G11C11/21
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