| 摘要 |
A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises a trade-off between power dissipation and area usage in data path allocation. Power dissipation and area constraints and a priority between them are input. An algorithm automatically decides the number of registers that are to be used, according to the specified priority and constraints specified. Power management formulations can be used to gear the allocation process to trade lower power management costs for equivalent savings in register areas. Multi-criteria optimisation Integer Linear Programming is utilised with heuristically determined power and area weightings to suit different predefined requirements of the chip design. Bipartite weighted Assignment is used to determine the number of registers to be used at every stage, through cost formulations and the Hungarian Algorithm.
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