| 摘要 |
PROBLEM TO BE SOLVED: To facilitate analysis of the cause of an error, even if the internal configuration or internal specifications of a logic system are not clear. SOLUTION: A verification apparatus for the logic system described in a hardware description language records information about the state of execution of a dynamic simulation about the logic system, while performing simulation. The verification apparatus creates information about internal expressions by converting the logic system. Should an error occur during the dynamic simulation, the verification apparatus searches for and presents the cause of the error involved in the logic system, based on the information about the state of execution and the information about the internal expressions. COPYRIGHT: (C)2006,JPO&NCIPI
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