| 摘要 |
Dynamic random access memory (DRAM) sensing is accomplished by using capacitive mismatch between a bit line without a cell and a corresponding bit line with a cell to determine if a selected capacitor holds a one or a zero. Isolators on the bit lines are used to create the mismatch. In this manner, reference cells and bit-line twisting are eliminated, while maintaining rail pre-charge at VDD or ground. Utilizing short bit-lines, 'Zero' (for GND pre-charge) can be sensed by means of inherent capacitive mis-match. The zero will hold the bit-line at GND, the bit-line without a cell (or with fewer cells) will have less capacitance and rise faster than the bit-line with the cell due to capacitive mis-match. For sensing a 'one', the bit-line will have enough signal to overcome the capacitive mis-match.
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