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发明名称
METHOD FOR SEPARATELY OPTIMIZING THIN GATE DIELECTRIC OF PMOS AND NMOS TRANSISTORS WITHIN THE SAME SEMICONDUCTOR CHIP AND DEVICE MANUFACTURED THEREBY
摘要
申请公布号
EP1668696(A4)
申请公布日期
2008.09.03
申请号
EP20040783206
申请日期
2004.09.07
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
CHOU, ANTHONY, I.;FURUKAWA, TOSHIHARU;VAREKAMP, PATRICK, R.;SLEIGHT, JEFFREY, W.;SEKIGUCHI, AKIHISA
分类号
H01L21/8238
主分类号
H01L21/8238
代理机构
代理人
主权项
地址
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