| 摘要 |
A delay locked circuit using a phase shifter and a delay locking method using the same are provided to generate an internal clock signal with the minimum skew error by generating a delay pulse and an internal clock through a clock signal and an inverted clock signal symmetrical to each other. A delay locked circuit(200) includes a time-digital converting unit(210), a phase shifter(220), a T/4 delayed pulse signal generating unit(230), and a clock reproducing unit(240). The time-digital converting unit converts an external clock signal into a digital signal corresponding to one period of the external clock signal and outputs a cyclic period information signal and a unit period information signal. The phase shifter receives the external clock signal and outputs a clock signal(CLK) having in-phase identical with the external clock signal and an inverted clock signal(CLK_B) having out-of-phase identical with the external clock signal. The T/4 delayed pulse signal generating unit receives the cyclic period information signal and the unit period information signal, generates a T/4 digital information signal corresponding to a 1/4 period of the external clock signal, and generates two T/4 delayed pulse signals(sync_qA,sync_qB) by using the T/4 digital information signal. The clock reproducing unit receives the two T/4 delayed pulse signals and generates an internal clock signal by delaying the external clock signal by a T/4 time. |
