发明名称 |
Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size |
摘要 |
A field programmable gate array includes a plurality of programmable logic blocks to implement one or more logic functions. The field programmable gate array includes a plurality of independent registers not associated with any specific one of the plurality of programmable logic blocks. The plurality of independent registers may be programmed to support any one of the plurality of programmable logic blocks.
|
申请公布号 |
US7420390(B1) |
申请公布日期 |
2008.09.02 |
申请号 |
US20060328407 |
申请日期 |
2006.01.09 |
申请人 |
ALTERA CORPORATION |
发明人 |
HUTTON MICHAEL D.;SCHLEICHER, II JAMES G. |
分类号 |
H03K19/177 |
主分类号 |
H03K19/177 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|