发明名称 |
Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof |
摘要 |
Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for geometric considerations of the semiconductor devices thereby allowing for a more flexible model and simulation by providing for geometric scaling capabilities.
|
申请公布号 |
US7421383(B2) |
申请公布日期 |
2008.09.02 |
申请号 |
US20030346048 |
申请日期 |
2003.01.15 |
申请人 |
TAIWAN SEMICONDUCTOR MFG CO, LTD |
发明人 |
HSIAO CHENG;SU KE-WEI;HER JAW-KANG |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|