发明名称 |
Semiconductor integrated circuit and leak current reducing method |
摘要 |
The present invention provides a semiconductor integrated circuit device which includes at least an SRAM memory cell array comprising a plurality of memory cells each constituted of a circuit including load MOS transistors, drive MOS transistors and transfer MOS transistors, a substrate bias generating circuit which is electrically connected to the load MOS transistors and supplies a substrate potential to the load MOS transistors during at least operation and standby, and a source bias generating circuit which is electrically connected to the drive MOS transistors and supplies a source potential to the drive MOS transistors at standby. It is possible to reduce a leak current in an SRAM memory cell during both operation and standby and reduce current consumption.
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申请公布号 |
US7420857(B2) |
申请公布日期 |
2008.09.02 |
申请号 |
US20060546955 |
申请日期 |
2006.10.13 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
HIROTA MAKOTO;KIKUCHI HIDEKAZU |
分类号 |
G11C11/34 |
主分类号 |
G11C11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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