| 摘要 |
A clock gated circuit is provided to reduce power consumption and a discharge time by preventing an unnecessary charge from being inputted into a fighting node in a discharging section. A clock gated circuit(500) includes a clock signal receiving unit(510), a discharge unit(520), a voltage maintaining unit(540), and an output unit(550). The clock signal receiving unit applies a first voltage to a fighting node in a section in which a gated clock signal has first logic. The discharge unit discharges a charge from the fighting node in transition of the clock signal from the first logic to second logic in a section in which an enable signal is activated. The voltage maintaining unit maintains a power voltage or a ground voltage of the fighting node. The output unit reverses a logic level of the voltage of the fighting node to output the voltage as the gated clock signal.
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