| 摘要 |
A sigma-delta modulator is supplied with a data word and includes a first and at least one further modulation stage, each having at least two adders. The adders in the first modulation stage process a low-significance component and a delayed more significant component of the data word and provide a result word and a carry at their respective outputs. The adders in the at least one further modulation stage process a low-significance component and a more significant component of the result word and provide a further result word and a carry at their respective outputs. The low-significance component and the more significant component of the result word are provided to the further modulation stages with an unvarying delay. A bit stream is derived from a carry from final instances of the at least two adders in the first modulation stage and in the further modulation stage respectively.
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