| 摘要 |
An apparatus for processing a video stream is provided to encode and decode stream data according to various video coding standards. An apparatus for processing a video stream includes firmware(110), a CPU(Central Processing Unit)(112), an H/W(Hardware) accelerator(114), an MUX(Multiplexer)(116), a data memory(118), a DMA(Direct Memory Access)(120), an FIFO(First-In First-Out)(122), an MUX(124), a host I/F(Interface)(126), and a register block(128). The DMA reads stream data from an external memory according to the control of the CPU. The H/W accelerator performs the decoding of the stream data from a buffer according to the control of the CPU. The buffer stores the stream data. The H/W accelerator includes plural decoders for decoding the stream data in a method suitable for plural video coding standards. |
