| 摘要 |
A semiconductor device for applying a well bias and a method for fabricating the same are provided to implement an upper transistor having an improved threshold voltage and minimizing a leakage current by forming a semiconductor plug between the upper transistor and the semiconductor substrate. A well contact forming region(106a) is provided on a semiconductor substrate. An interlayer dielectric(135) is formed on the well contact region. A semiconductor body layer(145) is formed on the interlayer dielectric. A transistor is provided on the semiconductor body layer. A well pick up region(133) is provided to the well contact forming region. Semiconductor plugs(140a,140b,140c) pass through the interlayer dielectric and are disposed between the transistor and the well pick up region. The semiconductor plugs have a conductive type identical to that of the well pick up region. The transistor includes a gate dielectric(150), a gate electrode(156), and source/drain regions(175). The gate dielectric and the gate electrode are laminated on the semiconductor layer in turn. The source/drain regions are provided on the semiconductor body layer at both sides of the gate electrode.
|
