| 摘要 |
<p>An address transition detector circuit includes an input node, an output node, a bandgap reference node, and P<SUB>bias </SUB>and N<SUB>bias </SUB>nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the P<SUB>bias </SUB>node and the N<SUB>bias </SUB>node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.</p> |
