发明名称
摘要 PROBLEM TO BE SOLVED: To reduce a circuit scale and to perform an efficient data correction by simultaneously performing data corrections of plural data processors. SOLUTION: This device is provided with a correction mode detection means 410 for detecting the mode of a correction to be executed to a data processing result based on at least two sets of state signals for indicating the state of a data processor and the output of an instruction decoder. A data correction control means 420 generates control signals for controlling the data correction from the output signals of the correction mode detection means 410. A data processing output means 430 executes the correction to the respective bits of the data processing result and outputs it or outputs the data processing result as it is corresponding to the control signals of the data correction control means 420.
申请公布号 JP4142143(B2) 申请公布日期 2008.08.27
申请号 JP19980019688 申请日期 1998.01.30
申请人 发明人
分类号 G06F7/00;G06F7/38 主分类号 G06F7/00
代理机构 代理人
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