发明名称 |
Constraint assistant for circuit design |
摘要 |
A computer aided design tool and method for designing IC layouts by recommending subcircuit layout constraints based upon an automated identification from a circuit schematic of subcircuit types requiring special IC layout constraints. Subcircuit types are identified on the basis of netlist examination, as well as cues from the layout of the circuit schematic.
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申请公布号 |
US7418683(B1) |
申请公布日期 |
2008.08.26 |
申请号 |
US20050233809 |
申请日期 |
2005.09.21 |
申请人 |
CADENCE DESIGN SYSTEMS, INC |
发明人 |
SONNARD JEAN-DANIEL;WANG ZHIGANG;SAMPATH HEMANTH |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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