发明名称 |
Method and apparatus for resetable memory and design approach for same |
摘要 |
A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupled to a resetable storage cell output that indicates whether a storage cell within the memory without reset capability has been written to after a reset or has not been written to after a reset.
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申请公布号 |
US7417888(B2) |
申请公布日期 |
2008.08.26 |
申请号 |
US20050184294 |
申请日期 |
2005.07.18 |
申请人 |
SYNOPSYS, INC. |
发明人 |
SESHADRI VIJAY K.;MCELVAIN KENNETH S. |
分类号 |
G11C7/00;G06F17/50;G11C5/00;G11C7/10 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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