| 摘要 |
A semiconductor memory device is provided to perform stable operation without operation error due to the lack of timing margin caused by the increase of physical length of a global data bus. A delay unit(100) delays a column-control signal in response to a write read signal. A write driving control unit(300) outputs a bank-column control signal and a write driving-control signal by receiving a bank-selection signal and an output signal of the delay unit. A column selection signal generation unit(200) outputs a plurality of column addresses to a corresponding column-selection signal in response to the bank-selection signal and the bank-column control signal. A write driving unit(420) drives data of a global data bus to a local data bus in response to the write driving-control signal. A bit line sense amplification unit(440) transfers data of the local data bus to a bit line in response to the column-selection signal.
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