POWER SAVING MULTI-WIDTH PROCESSOR CORE

摘要

A single core, multi-width merged architecture processor using industry standard instructions to provide power savings and higher performance at lower clock rates. The processor core has two separate decode blocks that share internal memory work space, memory management, and I/O processing. In normal functional mode the processor executes instructions using 8 bit wide data and instructions. In 8 bit mode the clock tree to the 32 bit functionality is held low to allow for low power operation. When additional processing power is required, the 32 bit decode blocks are enabled and the 8 bit functionality is disabled. The internal work context is shared between the two modes, so the same memory and registers are manipulated in either 8 bit or 32 bit modes. In a particular embodiment, the multi-width, merged architecture core is an embedded core using an industry standard, 8 bit register and interrupt architecture with a special 32 bit mode, providing an industry standard 16 bit instruction set with 32 bit data and register accesses to process the aforementioned 8 bit register architecture.

主权项

1. A variable width, merged architecture processor for increased functionality and power savings comprising:
a single load/store architecture industry standard processor core having a first decode unit and a second decode unit, with each decode unit having width, wherein the second decode unit is wider than the first decode unit, with each decode unit having access to a single, internal, load/store memory work area.