发明名称 Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package
摘要 In a method of manufacturing an electronic component package, first, there is fabricated a wafer incorporating a plurality of sets of external connecting terminals corresponding to a plurality of electronic component packages, and a retainer for retaining the plurality of sets of external connecting terminals, the wafer including a plurality of pre-base portions that will be separated from one another later to be bases of the electronic component packages. Next, at least one electronic component chip is bonded to each of the pre-base portions of the wafer. Next, electrodes of the electronic component chips are connected to the external connecting terminals. Next, the electronic component chips are sealed. Next, the wafer is cut so that the pre-base portions are separated from one another and the plurality of bases are thereby formed.
申请公布号 US2008197484(A1) 申请公布日期 2008.08.21
申请号 US20070706367 申请日期 2007.02.15
申请人 HEADWAY TECHNOLOGIES, INC.;SAE MAGNETICS (H.K.) LTD. 发明人 SASAKI YOSHITAKA;SHIMIZU TATSUSHI
分类号 H01L23/48;H01L21/00 主分类号 H01L23/48
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