IC PACKAGE WITH INTEGRAL VERTICAL PASSIVE DELAY CELLS
摘要
Multilayer semiconductor devices and methods for their assembly are described in which the IC packages are endowed with vertical passive delay cells (22a, 22b) in order to approximately equalize, within selected design tolerances, the signal propagation delays among electrical traces within the package (20).
申请公布号
WO2008083254(A3)
申请公布日期
2008.08.21
申请号
WO2007US88997
申请日期
2007.12.27
申请人
TEXAS INSTRUMENTS INCORPORATED;YUE, HEPING;LIANG, HONGWEI;LAMSON, MICHAEL, A.
