Memory power management

摘要

A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation.

主权项

1. A memory module, comprising:
a controller configured to initiate an autorefresh operation and to provide a clock signal and a clock control; and a plurality of volatile dynamic random access memory (DRAM) circuits, each DRAM circuit having:
a clock signal input; and a clock control comprising a state of enabled or disabled and the clock control is set to enabled during performance of a write operation, or a read operation,
wherein when the controller determines that the state of the clock control of the DRAM circuit is disabled and an autorefresh operation is to be performed, the state of the clock control is set to enabled and an autorefresh operation command is issued by the controller to the DRAM circuit to initiate an autorefresh operation of the DRAM circuit, and the state of the clock control is set to disabled after completion of the autorefresh operation; and, a transition between any one of the write operation, the read operation, or the autorefresh operation is made without performing a selfrefresh operation; andwherein the clock control state is disabled without performing a concurrent selfrefresh operation for the DRAM circuit.