| 摘要 |
A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2<SUP>N </SUP>configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2<SUP>N </SUP>tri-state buffers coupled to receive the 2<SUP>N </SUP>configuration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of control signals to control the 2<SUP>N </SUP>tri-state buffers so that one or more of the 2<SUP>N </SUP>configuration bit inputs is selected by the first stage. The configuration bits are then provided to subsequent muxing stages in the Look Up Table.
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