发明名称 |
Clock Pulse Duty Cycle Control Circuit for a Clock Fanout Chip |
摘要 |
A clock pulse duty cycle control circuit for receiving an input clock signal and for providing an output clock signal having a desired duty cycle. An error signal generator includes a differential integrator that is connected to receive the output clock signal. The differential integrator integrates the output clock signal to produce a time-varying DC error signal representative of a difference between the output clock signal duty cycle and the desired duty cycle. A duty cycle corrector includes a differential integrator connected to receive the input clock signal and the error signal. The differential integrator integrates the input clock signa to produce a correction stage clock signal. The differential integrator causes the slopes of the input clock signal edges to be adjusted as a function of the error signal. A buffer including a high gain amplifier is connected to receive the correction stage clock signal and squares the edges of the clock signal to produce the output clock signal.
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申请公布号 |
US2008197903(A1) |
申请公布日期 |
2008.08.21 |
申请号 |
US20060813844 |
申请日期 |
2006.01.13 |
申请人 |
MAYO FOUNDATION FOR MEDICAL EDUCATION AND RESEARCH |
发明人 |
HUMBLE JAMES S. |
分类号 |
H03K3/017 |
主分类号 |
H03K3/017 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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