发明名称 |
DMA LATENCY COMPENSATION WITH SCALING LINE BUFFER |
摘要 |
A video processing system configured with DMA latency compensation is disclosed. This compensation helps minimize or otherwise mitigate shortages of data to the display, thereby improving the quality of displayed video. A relatively small line buffer is used to stage data for video processing. Should an underflow of data occur (where the buffer reading process is ahead of the buffer writing process), data is read from the previous line buffer. This not only prevents shortages of data to the display, but also provides data that is more likely to be relevant to the actual scene being displayed (as compared to random data).
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申请公布号 |
WO2006063337(A3) |
申请公布日期 |
2008.08.21 |
申请号 |
WO2005US44885 |
申请日期 |
2005.12.09 |
申请人 |
WIS TECHNOLOGIES, INC.;SHA, LI;HUANG, QIFAN |
发明人 |
SHA, LI;HUANG, QIFAN |
分类号 |
G06F17/00;G06F13/28;G06T1/00;G06T1/60;G09G5/00;G09G5/36 |
主分类号 |
G06F17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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