| 发明名称 |
METHOD FOR USING DIGITAL PLL IN A VOLTAGE REGULATOR |
| 摘要 |
A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.
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| 申请公布号 |
US2008197830(A1) |
申请公布日期 |
2008.08.21 |
| 申请号 |
US20070951565 |
申请日期 |
2007.12.06 |
| 申请人 |
INTERSIL AMERICAS INC. |
发明人 |
MEHAS GUSTAVO JAMES;AGARWAL SANDEEP;VIVREKAR JAYANT;CHEN XIAOLE |
| 分类号 |
H03L7/085;G05B24/02 |
主分类号 |
H03L7/085 |
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