发明名称 METHOD AND APPARATUS FOR MEASURING PIPELINE STALLS IN A MICROPROCESSOR
摘要 A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares the number of stall cycles to the deterministic execution latency pattern. The process identifies the instruction as a dependent instruction in response to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed.
申请公布号 US2008201566(A1) 申请公布日期 2008.08.21
申请号 US20070675112 申请日期 2007.02.15
申请人 发明人 INDUKURU VENKAT RAJEEV;MERICAS ALEXANDER ERIK
分类号 G06F9/38 主分类号 G06F9/38
代理机构 代理人
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