LAYOUT DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To solve the problem that an inter-wiring capacitance value is changed since a dummy metal is inserted to a layout after timing is matched after the end of layout routing processing when preparing a mask required for manufacturing a semiconductor device, timing design is required again and a design period (TAT) from the end of the layout routing processing to mask preparation becomes long. SOLUTION: From the stage of the layout routing processing, a wirable area rate is given to a region excluding existing wiring for an arbitrary unit area, and layout design is performed in consideration of timing and a process area rate. COPYRIGHT: (C)2008,JPO&INPIT