发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which includes a plurality of cell blocks equipped with standard cells different in cell height, and can reduce a clock skew among the cell blocks. SOLUTION: The semiconductor integrated circuit includes a standard cell 109 and a standard cell 110 different in cell height from the standard cell 109. A pair of N-type diffusion regions 205 and a P-type diffusion region 207 for supplying first substrate power supply to a standard cell 105 are provided on a P-well region 201 of the standard cell 109. A pair of N-type diffusion regions 205 and a P-type diffusion region 207 for supplying second substrate power supply to a standard cell 110 are provided on the P-well region 201 of the standard cell 110. A distance between the N-type diffusion region 205 and the P-type diffusion region 207 of the standard cell 109 is substantially the same as a distance between the N-type diffusion region 205 and the P-type diffusion region 207 of the standard cell 110. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008192841(A) 申请公布日期 2008.08.21
申请号 JP20070025952 申请日期 2007.02.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NOZOE MITSUYOSHI
分类号 H01L21/82 主分类号 H01L21/82
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