| 摘要 |
PROBLEM TO BE SOLVED: To efficiently carry out DMA (direct memory access) transfer to avoid mismatching caused by continuously occupying a data bus by a specific module. SOLUTION: A period value of a DMA interval indicating an interval until a following DMA request is made after the completion of DMA transfer by any one of DMA modules 12-0 to 12-n is set to registers 12-0a to 12-na in the respective DMA modules. When a plurality of DMA requests out of the respective DMA modules 12-0 to 12-n concur, DMA transfer permission is given to the DMA request from the DMA module 12-1 with high priority, for instance, by a DMA bus arbitration circuit 14, and after the completion of the DMA transfer, the occurrence of the following DMA request from the DMA module 12-1 is restrained until meeting all the DMA requests from the DMA modules 12-0, 12-2 and 12-3 other than the DMA module 12-1 whose DMA transfer is completed. COPYRIGHT: (C)2008,JPO&INPIT
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