50 Gb/s Ethernet using serializer/deserializer lanes

摘要

Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

主权项

1. A device comprising:
circuitry configured to
receive Ethernet frames on each of a plurality of serializer/deserializer (SERDES) lanes at a M/N Gb/s rate, where M is a value greater than or equal to 10 and N is a number of the SERDES lanes;bond the SERDES lanes into a stream of received Ethernet frames; andprovide data from the bonded stream of Ethernet frames to a MAC port having an M Gb/s rate.