| 摘要 |
A non volatile memory device is provided to reduce load of a bit line by improving the structure of a memory cell array and the structure of the bit line by performing well bias quickly. A top memory cell array and a bottom memory cell array are controlled by an equal page buffer. A top bit line selection part(220) controls connection between top bit lines connected to a memory cell of the top memory cell array and a sensing node of the page buffer. A bottom bit line selection part(222) controls connection between bottom bit lines connected to a memory cell of the bottom memory cell array and the sensing node of the page buffer.
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