发明名称 PER BYTE LANE DYNAMIC ON-DIE TERMINATION
摘要 A dynamic on-die termination on respective byte lines is provided to improve signal quality for interconnecting integrated circuits with each other by matching impedances to minimize signal reflection. Plural integrated circuits(110,120-A,120-N) are interconnected with each other. An ODT(On-Die Termination) control logic(112) independently programs ODT values for the respective ICs. The ODT value specifies an amount of a termination resistance. The IC includes plural DRAMs integrated in a memory system(100). The ODT control logic includes a DRAM(Dynamic Random Access Memory) ID determining logic and a DRAM ID programming logic. The DRAM ID determining logic determines the DRAM IDs for the respective DRAMs, which correspond to a length of a byte line. The DRAM ID programming logic programs the determined DRAM ID in respective DRAM registers in the memory system.
申请公布号 KR20080076851(A) 申请公布日期 2008.08.20
申请号 KR20080014158 申请日期 2008.02.15
申请人 INTEL CORP. 发明人 COX CHRISTOPHER;FAHMY HANY;OIE HIDEO
分类号 G11C7/10 主分类号 G11C7/10
代理机构 代理人
主权项
地址
您可能感兴趣的专利