| 摘要 |
An apparatus and a method for controlling a reception clock error in a high speed baseband data storage data system are provided to minimize a clock timing error of a frame clock between all memory boards. An apparatus for controlling a reception clock error in a high speed baseband data storage data system includes a clock generation unit(210), a clock distribution unit(220), a plurality of memory boards(230,240,250), and a control unit(270). The clock generation unit generates a first reference clock, a second reference clock and a third reference clock. The clock distribution unit generates a fourth reference clock by distributing a first reference clock, and generates a fifth reference clock by distributing a second reference clock. The memory boards receive the fourth reference clock as an operation clock, and receive the fifth reference clock as a clock for determining a start and an end of data. The memory boards generate a sixth reference clock, and provide a clock error of the fifth reference clock and the third reference clock. The memory boards receive a clock error correction command, correct the clock error, and input/output the data in response to the command. The control unit is coupled to the memory boards in parallel, and receives the clock error of each of the memory boards. The control unit commands the correction of the clock error based on the clock error of the memory board having a largest error, and performs a memory access for a baseband data input/output of a high speed.
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