发明名称 Pitch doubled circuit layout
摘要 In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry includes providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further includes elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.
申请公布号 US7413981(B2) 申请公布日期 2008.08.19
申请号 US20050192828 申请日期 2005.07.29
申请人 MICRON TECHNOLOGY, INC. 发明人 TANG QIANG;GHODSI RAMIN
分类号 H01L21/44 主分类号 H01L21/44
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