发明名称 |
Coverage circuit for performance counter |
摘要 |
A coverage circuit for use with a general purpose performance counter ("GPPC") connected to a bus for capturing test coverage information encoded as N one-hot signals indicative of coverage in a logic design. An OR logic block is included for bit-wise ORing the N one-hot signals with a N-bit mask value stored in a register block so that an N-bit output may be generated by the OR logic block depending on the logic transitions of the one-hot signals. A Multiplexer (MUX) block is provided for selecting the N-bit output from the OR logic block under control of at least one control signal, wherein the N-bit output is operable to be stored into the register block when selected by the MUX block.
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申请公布号 |
US7415643(B2) |
申请公布日期 |
2008.08.19 |
申请号 |
US20030635371 |
申请日期 |
2003.08.06 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
ADKISSON RICHARD W. |
分类号 |
G01R31/28;G06F11/00;H02H3/05 |
主分类号 |
G01R31/28 |
代理机构 |
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