发明名称 DMA completion processing mechanism
摘要 According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.
申请公布号 US7415549(B2) 申请公布日期 2008.08.19
申请号 US20050237455 申请日期 2005.09.27
申请人 INTEL CORPORATION 发明人 VEMULA KIRAN;LAU VICTOR;SETO PAK-LUNG;CHANG NAI-CHIH;HALLECK WILLIAM;CHEMUDUPATI SURESH;PARIKH ANKIT;TSAO GARY Y.
分类号 G06F13/28;G06F13/00 主分类号 G06F13/28
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