| 摘要 |
A delay apparatus, a delay locked loop circuit and a semiconductor memory apparatus using the same are provided to improve operation performance of a delay locked loop by performing accurate and stable delay lock operation regardless of the variation of PVT(Process, Voltage, Temperature). A plurality of unit delays(410-412) receive an output signal of a former stage. A signal input part(420) inputs an input signal to one unit delay corresponding to an initial state selection signal among the plurality of unit delays. An initial state selection part(430) generates the initial state selection signal in response to an initial state setting signal, and then outputs the initial state selection signal to the signal input part. The signal input part comprises a plurality of logic devices inverting an input signal and then outputting the inverted input signal to each unit delay according to the initial state setting signal.
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